- Job Responsibilities:
- In Charge of entire Digital Back-end Physical Design & automation (from netlis-to-GDS)
- Main responsibilities include circuit synthesis, physical synthesis, static timing analysis, chip Floorplanning, auto place and route, capacitance and resistance extraction, design rule checking and delay back-annotation
- Responsible for clock tree synthesis, scan chain generation, critical path timing analysis and power analysis
- DRC/LVS command file writing and maintenance
Requirement:
- Masters Degree in Electrical/Computer Engineering
- At least a solid 3 years experience in physical design with tapeouts
- Must demonstrate proven knowledge of complete Netlist-to-GDS flow, including floor planning, power-grid synthesis, place opt. and routing, CTS, timing closure, signal integrity, STA, and physical verification
- Hands-on knowledge of Synopsys/Cadence tools like ICC or Encounter is required
- Possess expertise in low power design implementation or flow development
- Experience in hierarchical design implementation is a plus
- Good in script programming with Perl, TCL/TK or other languages
Interested Candidates, Please send your resume to devi@uniconnect.com.sg
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