Location: Singapore
Experience: 5 - 20 Years
Job Description:
Handled Netlist to GDS II at block level for multiple tape outs.
Hands-on experience on technology nodes like 28nm, 20nm, 14nm, 10nm
Good knowledge of EDA tools from Synopsys , Cadence and Mentor, particularly experience with ICC, PTSI, Encounter, Nanoroute, Calibre, StarRC
Hands-on experience in floor planning, placement optimizations, CTS and
routing.
Hands-on experience in block/top level signoff STA, physical verification (DRC/LVS/ERC/antenna) checks and other reliability checks(IR/EM/Xtalk)
Exposure in physical implementation of timing/functional ECOs
Good knowledge of VLSI process and device characteristics TCL, perl scripting
Share your CV to priyanka.s@sevitechsystems.com
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