Design Engineer for Hexosys Sdn Bhd, Malaysia

5+ years experience

• Design and Verification of FPGAs with Verilog/VHDL
• Optimizing FPGA code to minimize resources / maximize clock speed.
• Verification of FPGAs using ModelSim, etc.
• Debug FPGA issues on the hardware platform
• Invent, document, and implement micro-architecture and design details for new-product features.
• Physical implementation in FPGA targets for emulation; timing closure, debug

• Outstanding hands on FPGA design and development experience on either Altera or Xilinx
• Expert experience with Verilog (or possibly VHDL) RTL design and high-speed digital design methodologies.
• FPGA Code development / design experience with either Xilinx ISE Foundation or Altera Quartus II
• FPGA Verification & Debug experience using ModelSim, (Perl, Python).
• Experience in floor planning, synthesis, and placement & routing; Xilinx and Altera is ideal
• Experience with writing BFM, monitors (PCI/PCIe, USB, and DDR2/3) and test benches.
• Extensive packet processing experience as well as full-chip verification

Recruiter Name:Komal Srivastava

Website:http://www.HexoSys.com

Email Id:komal.srivastava@naukri.com